1. Field of Invention
The present invention relates to a transmission device that conforms to the HDMI (High-Definition Multimedia Interface) that is used in Blu-ray/DVD (digital versatile disc) players and Blu-ray/DVD recorders for simultaneously transmitting digital video signals and digital audio signals.
2. Description of Related Art
Transmitters and receivers that conform to the HDMI specification are rapidly increasing in popularity as input/output interface devices for easily sending and receiving high-definition video signals and high-definition audio signals.
FIG. 4 is a block diagram of a transmission and reception system conforming to the HDMI specification, that is, that uses an HDMI interface. This transmission and reception system using a HDMI interface includes a transmission device 81p, an HDMI cable 83p, and a reception device 82p. The transmission device 81p digitally transmits digital video signals and digital audio signals to the reception device 82p over the HDMI cable 83p. A transmission device 81p according to the related art is taught in Japanese Laid-open Patent Publication No. 2004-23187.
FIG. 5 is a block diagram of a transmission section of an audio signal in a transmission device 81p according to the related art. As shown in FIG. 5 this transmission device 81p has a parameter value selection unit 13p, a frequency divider 11p, a counter 12p, a content signal generating unit 15p, and a physical layer format conversion unit 14p. 
The parameter value selection unit 13p selects a specific parameter value from among a plurality of parameter values, and generates and outputs a selected parameter value Np representing the selected parameter value to the frequency divider 11p and content signal generating unit 15p. 
Node TDAp receives the digital audio signal DAp, and node TDPp receives the digital video signal DPp.
Node TSAp receives audio clock SAp representing the master clock for processing the digital audio signal DAp.
Node TSPp receives the pixel clock SPp representing the master clock for processing the digital video signal DPp.
The frequency divider 11p frequency divides the audio clock SAp using the selected parameter value Np, and outputs frequency division signal SADp. If the frequency of the audio clock SAp (that is, the audio clock frequency) is FAp, the frequency of the frequency division signal SADp (that is, the frequency division signal frequency) FADp is shown by the following expression.FADp=FAp/Np 
The counter 12p counts each cycle of the frequency division signal SADp at the pixel clock SPp, generates the cycle time stamp CTSp representing the resulting count, and outputs to the content signal generating unit 15p. If the frequency of the pixel clock SPp (that is, the pixel clock frequency) is FPp, the cycle time stamp CTSp is shown by the following expression.CTSp=FPp/FADp 
The content signal generating unit 15p includes buffer memory not shown. The content signal generating unit 15p compresses the time base by writing the digital audio signal DAp, selected parameter value Np, and cycle time stamp CTSp at the audio clock SAp to buffer memory, and then reading at the pixel clock SPp. The content signal generating unit 15p packetizes and inserts the time-base-compressed digital audio signal DAp, selected parameter value Np, and cycle time stamp CTSp to the blanking period of the digital video signal DPp. The content signal generating unit 15p thus produces a content signal SCp representing the inserted signal, and outputs to the physical layer format conversion unit 14p. 
The physical layer format conversion unit 14p converts the content signal SCp and pixel clock SPp to the physical layer format of the TMDS (Transition-Minimized Differential Signaling) specification to produce and output a physical layer conversion signal STp representing the converted signal to the reception device 82p. The transmission device 81p thus does not send the audio clock SAp directly to the reception device 82p, and instead sends the cycle time stamp CTSp and selected parameter value Np representing information about the audio clock SAp relative to the pixel clock SPp to the reception device 82p. The reception device 82p then generates the audio clock SAp based on the pixel clock SPp, selected parameter value Np, and cycle time stamp CTSp.
If the sampling frequency of the digital audio signal DAp (that is, the audio sampling frequency) is FSp, the audio clock frequency FAp is shown by the following expression.FAp=128*FSp 
FIG. 6 is a block diagram showing a part of the reception device 82p. The reception device 82p receives the pixel clock SPp, selected parameter value Np, and cycle time stamp CTSp from the transmission device 81p over the HDMI cable 83p, and outputs the playback audio clock SA1p. 
Based on the received cycle time stamp CTSp, the frequency divider 61p generates a playback frequency division signal SAD1p, which is the pixel clock SPp frequency divided using the cycle time stamp CTSp. The frequency of the playback frequency division signal SAD1p (that is, the playback frequency division signal frequency) FAD1p is shown by the following expression using the pixel clock frequency FPp.FAD1p=FPp/CTSp 
The N multiplier 66p is a PLL (Phase Locked Loop), and includes a phase detector 62p, LPF (low pass filter) 63p, VCO (variable phase oscillator) 64p, and N frequency divider 65p. 
The N multiplier 66p multiplies the playback frequency division signal SAD1p Np times, and outputs the playback audio clock SA1p. If the sampling frequency of the reproduced digital audio signal DAp (that is, the playback audio-sampling frequency) is FS1p, the frequency FA1p of the playback audio clock SA1p (that is, the playback audio clock frequency) is shown by the following expression.
                              FA          ⁢                                          ⁢          1          ⁢          p                =                  FAD          ⁢                                          ⁢          1          ⁢          p          *          N          ⁢                                          ⁢          p                                        =                  128          *          Fs          ⁢                                          ⁢          1          ⁢          p                    
As described in Design Wave Magazine (pp. 73-81, April 2008, CQ Shuppansha), the selected parameter value Np is greater than or equal to FA/1500 Hz and is less than or equal to FA/300 Hz as shown by the following expression.(FAp/1500 Hz)≦Np≦(FAp/300 Hz)
Within the range of the selected parameter value Np, if the audio sampling frequency FSp is 48 kHz, for example, the recommended selected parameter value Np is Np=(FAp/1000 Hz), and if the audio sampling frequency FSp is 44.1 kHz, the recommended selected parameter value Np is Np=(FAp/900 Hz).
The related art described above cannot, however, achieve sufficiently high performance audio quality. A transmission and reception system using the HDMI interface suffers from inferior sound quality compared with the IEC60958 specification, for example. As described above, the recommended selected parameter value Np is Np=(FAp/1000 Hz) when the sampling frequency is 48 kHz, and is Np=(FAp/900 Hz) when the sampling frequency is 44.1 kHz. These recommended values are premised on no change in the cycle time stamp CTSp over time.
In an actual transmission device 81p, however, the audio clock SAp and pixel clock SPp are generated based on two different reference clock generators (such as crystal oscillators). In such a configuration the frequency and phase of both clocks are independent of each other, and vary over time with differences in the temperature characteristics of the crystal oscillators. As a result, the cycle time stamp CTSp that is produced based on the audio clock SAp and pixel clock SPp varies over time. The playback frequency division signal frequency FAD1p therefore also varies over time. As a result, variation in the playback audio clock frequency FA1p is multiplied Np times by the N multiplier 66p, and thus varies even more greatly over time.